USF Bellini College of Artificial Intelligence, Cybersecurity and Computing Associate Professor Hao Zheng has received an NSF grant and a Best Paper Award from for developing a new framework for System-on-Chip (SoC) design validation with a focus on analyzing cross-block communications within SoC designs to reduce validation complexity. It will enable efficient and comprehensive validation of SoC designs through the entire design flow, leading to substantially improved productivity and quality of SoC validation, ultimately providing greater assurance in the deployed SoC designs.
鈥淭his project is actually the result of my long-time collaboration with the Intel Research Lab,鈥� said Zheng. 鈥淚 spent a summer visiting the Intel Lab 10 years ago to start my research on post silicon validation and since then we also collaborated on some other projects like using machine learning to infer system-level protocols from SoC execution traces to facilitate various validation activities.鈥�
They integrate these disciplines to foster a comprehensive approach to excellence in design. The rapid growth of computer systems relies on increasingly complicated SoC designs. As a solution to meet the mounting demand for new functionalities under aggressive time-to-market constraints, an SoC integrates hundreds of pre-designed hardware 鈥榖locks鈥� (IPs) that coordinate through sophisticated system-level protocols to realize various system functions. SoC designs must undergo comprehensive and rigorous validation to ensure safety and security before deployment in critical applications.
鈥淚 don't have an exact number about bugs in SoC designs, but I would say it's highly likely most have a few because of the high competition in the computer industry and sheer complexity of modern SoC designs.鈥� said Zheng.
鈥淐ompanies have to get their products to the market under very strict deadlines. To do that, SoC designs are typically realized by integrating many hardware IP blocks purchased from third parties, which may not be trusted. These components may contain errors or vulnerabilities due to design mistakes or malicious modifications. Current methods and tools are not able to provide comprehensive and rigorous validation under aggressive deadlines, therefore the chance of bugs escaped into final products cannot be ignored.鈥�
If design bugs and vulnerabilities are left undetected and not fixed, malicious actors could exploit them to bypass the implemented security defense measures, performing malicious activities including leaking secrets or cause system malfunctions.. This research aims to address that challenge.
In general, SoC validation goes through two stages. In the pre-silicon stage, SoC design models are verified. Technically, it has full observability, however, the full system validation is infeasible due to extremely slow simulation speed. In the post-silicon stage, validation is performed on silicon prototypes of the SoC designs. Since the silicon prototype runs at the target clock speed, post-silicon validation can run actual software, such as Micsosoft Office. However, it suffers from the 鈥榣imited observability problem鈥�, as the internal states of the chip are very difficult to probe and observe externally.
鈥淎n SoC chip may contain a billion of transistors and millions of wires. If anything goes wrong, then we often have to guess what happens inside the silicon as a SoC chip can offer at most a couple of hundreds of pins on the chip interface to observe those millions of internal wires.鈥� said Zheng. This limited observability is a huge challenge for post silicon validation.
Zheng鈥檚 research relies on analyzing intricate communications among hardware blocks to mitigate such challenges. Prior studies have shown that cross-block communications are a major source of errors and vulnerabilities. 鈥淥ne key challenge was ensuring our method scaled to complex, concurrent SoC communication traces while maintaining high accuracy,鈥� said Bardia Nadimi, a doctoral student who is also a machine learning intern at Cognichip Inc. Their research project consists of three tasks:
- Develop solutions to facilitate efficient and comprehensive pre-silicon full system validation based on a communication-centric methodology.
- Develop approaches to learning system communication models from the SoC execution traces generated during the full system validation to facilitate analysis and debug.
- Develop new machine learning methods utilizing the communication models from Task 2 to enhance the observability of the post-silicon traces for more efficient post-silicon debug
鈥淭his project deepened our appreciation for how much manual effort goes into system validation. Automating parts of that process felt incredibly rewarding,鈥� said Nadimi.
The National Science Foundation isn鈥檛 the only one to fund this research. Intel has provided seed funding, including $60,000 to support research on communication-centric post-silicon debugging and $120,000 to support research on inferring system-level communication protocols using machine learning.
鈥淢y collaboration with the Intel Strategic CAD Lab, now part of the Intel Lab, started in 2014 when I spent the summer in that lab with Dr. Jin Yang and his team. This collaboration has been fruitful.鈥�
Zheng is currently accepting applications for research positions in his lab. To apply, visit